ISL97801
TABLE 4. BOOST MODE COMPENSATION 12V OPERATION
VOUT (V)
7
10.5
14
17.5
21
24.5
28
VFB
I OUT
LED’s
2
3
4
5
6
7
8
50mV
50mA
Electrolytic
Ceramic
DMIN
DMIN
DMIN
60μF
40μF
40μF
40μF
100mV
100mA
Electrolytic
47μF
47μF
Ceramic
DMIN
DMIN
DMIN
40μF
20μF
40μF
40μF
200mV
350mA
Electrolytic
47μF
47μF
Ceramic
DMIN
DMIN
DMIN
40μF
20μF
40μF
40μF
200mV
1A
Electrolytic
47μF
47μF
Ceramic
DMIN
DMIN
DMIN
20μF
20μF
40μF
40μF
A Note about Ceramic Capacitors:
Many ceramic capacitors have strong voltage and
temperature coefficients which reduces effective
capacitance as the applied voltage or operating temperature
is increased. Pay careful attention when selecting ceramic
capacitor type. X5R and X7R families provide much better
stability than Y5V, which should generally be avoided unless
additional capacitance is added to compensate for the
significant changes in value which occurs over voltage and
temperature.
TABLE 5. CERAMIC CAPACITOR VARIABILITY
? Feedback signals levels are small to improve efficiency.
Ensure the reference connection (GND or VIN) between
the sense resistor and IC pin doesn't carry switching
current.
? Place several via holes (thermal vias) under the chip to a
backside ground plane to improve heat dissipation
? Maximize the copper area around the thermal vias to
spread heat away from the chip.
Cost-Sensitive Applications
For cost-sensitive applications, the BOM can be reduced
considerably by:
CAPACITOR TYPE
X7R, 10V
X5R, 25V
Y5V, 6.3V
TYPICAL VOLTAGE
VARIATION
-30% at 10V
-50% at 25V
-90% at 6.3V
TEMPERATURE
VARIATION
-15% at +125°C
-9% at +85°C
-65% at +85°C
1. Removing temperature compensation
2. Removing the fault-protection switch
3. Removing the load isolation switch
4. Switching the FB into internal fixed bias mode (400mV
across V FB )
Layout Considerations
PCB layout is very important for the converter to function
properly. The following general guidelines should be
followed:
? Separate the Power Ground and Signal Ground; connect
them only at one point close to the GND pin.
? Maximize the Power Ground area as much as possible. It
is essential to ensure th Power Ground return between
Cin, Cout, and SWS1,2 as least obstructive as possible.
? Place the input capacitor close to VIN and SWS1,2 pins in
boost mode.
? Make the following PC traces as short as possible:
- from SWD1,2 to the inductor in boost mode
- from SWS1,2 to the inductor in buck mode
- from Cout to PGND
15
In this configuration, light level may be controlled using the
EN/PWM input to modulate the output current.
In the absence of the load isolation switch, LED bias current
will vary with PWM duty cycle, due to the discharge of the
output capacitor by the LED’s during the PWM off time
therefore low dimming frequencies can only be used in such
application.
FN6428.1
April 2, 2007
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